Three dimensional (3D) packaging is employed in the microelectronics industry for stacking integrated circuits and thereby conserving space, increasing bandwidth, and reducing latency to boost the performance of silicon chips. In some 3D packages, through-silicon vias provide a means for forming electrical connections between circuits. Interposers containing vias are used between chips in some applications.
Via conductors are employed in electronic device packages to provide electrical connections between stacked dies or chips and/or other elements such as interposers. Vias are formed through substrates such as silicon wafers and filled with electrically conductive materials. Deep reactive ion etching ((DRIE) is a technique for forming high aspect ratio (relatively high depth to diameter) holes in silicon wafers. The via diameter ranges from 2-100 μm, with ranges of 5-50 μm being commonly employed. The via depth is from 10-500 μm, with ranges 30-300 μm being used in a number of applications. The aspect ratio is 3-30. Electroplating is one technique that is sometimes employed to form electrical conductors within vias. Pulsed plating, special plating solution and special tools are employed to ensure plating quality in high aspect ratio vias. Copper is among the materials electroplated to form via conductors in some applications. Vias can also be filled with solder or copper paste to form electrical conductors, though the current carry capability of conductors formed using solder or copper paste may be relatively limited. Copper paste includes copper particles and polymeric resin. The relatively small point contact areas among the copper particles limit the current carry capability thereof. Solder paste consists of solder powder (e.g. tin particles) and flux, resulting in volume shrinkage during reflow that should be addressed. The use of solder or copper paste within high aspect ratio vias entails the need to fill the vias with minimum resin and without voids.